This is a microMVP card.

10.000 MHz XTAL.

Three boot ROMs, labeled

    L39: @ WANG /87   == 6789-L29 (except for bytes 5&6)
	 377-3139 R1
    L50: @ WANG /87   == 6789-L28
	 377-3138 R1
    L58: @ WANG /87   == 6789-L27
	 377-3137 R1

These aren't EPROMs.  I peeled the label off of L39 and there is no window.
The logo looks kind of like black H on a white square -- perhaps Harris?
    M1-76161-5

The 6789 (VP) card has three 2708 EPROMs.

Comparing the first byte of these boot ROMs vs what the emulator is using
for the VP boot RAMs, the mapping seems to be
    L39 is the ls ucode byte
    L50 is the middle ucode byte
    L58 is the ms ucode byte
however, the ROM contents aren't identical.

Below, "||" means this pin is wired in parallel across all three chips

                       2708 pinout  2716 pinout  2732 pinout                   
                       -----------  -----------  -----------                   
    pin  1 - ||,           A7           A7           A7                   
    pin  2 - ||,           A6           A6           A6                   
    pin  3 - ||,           A5           A5           A5                   
    pin  4 - ||,           A4           A4           A4                   
    pin  5 - ||,           A3           A3           A3                   
    pin  6 - ||,           A2           A2           A2                   
    pin  7 - ||,           A1           A1           A1                   
    pin  8 - ||,           A0           A0           A0                   
    pin  9 - data          D0           D0           D0                   
    pin 10 - data          D1           D1           D1                   
    pin 11 - data          D2           D2           D2                   
    pin 12 - gnd           gnd          gnd          gnd                   
    pin 13 - data          D3           D3           D3                   
    pin 14 - data          D4           D4           D4                   
    pin 15 - data          D5           D5           D5                   
    pin 16 - data          D6           D6           D6                   
    pin 17 - data          D7           D7           D7                   
    pin 18 - ||,           Vpp/!ce      !ce/pgm      !en       <<< some confusion here on the 2716 pin function
    pin 19 - ||,           +12V         A10          A10                   
    pin 20 - ground        !oe/we       !oe          vpp/!oe                   
    pin 21 - ground        -5V          Vpp          A11                   
    pin 22 - ||,           A9           A9           A9                   
    pin 23 - ||,           A8           A8           A8                   
    pin 24 - +5V           +5V          +5V          +5V                   

pin 18 is connected pin 19!
pin 19 is connected to L57/11 (74S08), which is an AND gate output.
Thus, these are probably output enables, probably active low, or perhaps
a ROM output latch/clock.

dumprom.bs2 is a variation of the my dump2708.bs2 program.
the difference is that pins 20&21 are grounded, and 18&19 are driven by
the B10 output port.

It has 12 Hitachi HM6264LP-12 (8Kx8) SRAMs; obviously this is the microstore.
In total, it is 32Kx24b.  There is room for another 12 SRAMs, but they are
unpopulated.

There are 18 Seimens 41256 DRAMs (256Kx1).  This is the data store, and
in total is 512KB, with parity.

The main 121 pin PGA ASIC (13x13 grid, with a 7x7 square of pins in the middle
removed, except one pin in the corner of this interior) is L55, with this label:

    8724V
    VH457
    VC2043
    WL3014
    (c) WANG 84

There is another 48 pin DIP ASIC, L69, labeled:

    VTI
    536 VA   8271
    VL4501A-15PC
    KOREA A
